Method for Fabricating Corrugated Gate Dielectric-Semiconductor Interface Transistor
Introducing micro/nano-meter-scale corrugations on the gate dielectric of transistors, particularly thin-film field-effect transistors
Today’s trend in semiconductor chip manufacturing involves the miniaturization of transistors and increasing the density of transistors per integrated circuit. Researchers at University of Colorado Boulder have developed a corrugated gate dielectric-semiconductor interface that can be easily incorporated into the existing semiconductor manufacturing technology to improve the transistor device performance.
The invention involves the introduction of micrometer- or nanometer-scale corrugations on the gate dielectric of transistors, particularly thin film field-effect transistors. The team call this device a corrugated gate dielectric-semiconductor interface transistor. The corrugations can be patterned using semiconductor processing techniques, such as ultraviolet (UV) photolithography, electron beam lithography or nanoimprint lithography. The patterns are subsequently etched using reactive ion etching (RIE) and atomic layer etching (ALE) to produce the final corrugated gate dielectric layer. The presence of corrugations that run parallel to the length of the semiconductor channel from source to drain results in enhanced transistor device performance, specifically improved in the “on” state drain current, higher on/off ratio and higher charge transport mobility compared to conventional planar gate dielectric transistors.
Stage of Development
Available for exclusive or non-exclusive licensing.
- Provisional patent filed
- Provisional patent
- Patent application submitted